VHDL literal - 표현, 선언 예

reference : http://www.ics.uci.edu/~jmoorkan/vhdlref/literals.html

상수

constant FREEZE : integer := 32;
constant TEMP : real := 32.0;
constant FLAG :bit_vector(0 to 7) := "11111111";
constant MSG : string := "Hello";

숫자 표현

BIT_8_BUS <= B"1111_1111";
BIT_9_BUS <= O"353";
BIT_16_BUS <= X"AA55";

문자열로 상태정의해서 사용하기

type MY_LOGIC is ('X','0','1','Z');
type T_STATE is (IDLE, READ, END_CYC);
signal CLK : MY_LOGIC := '0';
signal STATE : T_STATE := IDLE;

배열

type NIBBLE is array (3 downto 0) of std_ulogic;
type MEM is array (0 to 7) of NIBBLE;
-- an array "array of array" type
variable MEM8X4 : MEM;
...
-- accessing the whole array:
MEM8X4 := ("0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111");
-- accessing a "word"
MEM8X4(5) := "0110";
-- accessing a single bit
MEM8X4(6) (0) := '0';